Printed circuit assemblies (PCA's) are typically tested after manufacture to verify the continuity of traces between pads and vias on the board and to verify that components loaded on the PCA perform within specifications. Such printed circuit assembly testing is generally performed with automated in-circuit testers or ICT's and requires complex tester resources. The tester hardware must generally be capable of probing conductive pads, vias and traces on the board under test.
In-circuit testers (ICT) have traditionally used “bed-of-nails” (BON) access to gain electrical connectivity to circuit wiring (traces, nets, pads) for control and observation capability needed for testing. This necessitates having access points within the layout of circuit nets that can be targets for ICT probes. Test access points are usually circular targets with 28 to 35 mil diameter that are connected to traces on the printed circuit board. In some cases these targets are deliberately added test pads, and in other cases the targets are “via” pads surrounding vias already provided in the printed circuit.
Lower diameter targets are increasingly difficult to hit reliably and repeatably, especially when a test fixture may contain several thousand such probes. It is always desirable to use larger diameter targets, but this is in fundamental conflict with the industry trend towards higher densities and smaller geometry devices.
Yet another industry trend is to use higher and higher speed logic families. One Megahertz (MHz) designs became ten MHz designs, then 100 MHz designs, and are now reaching the Gigahertz domain. The increases in logic speed necessitate industry attention to board layout rules for higher-speed interconnects. The goal of these rules is to create a controlled impedance pathway that minimizes noise, crosstalk and signal reflections. Printed circuit boards traces that carry high-speed signals tend to have critical layout requirements and require controlled characteristic impedances. When traditional test probe targets are added, this causes discontinuities in the controlled impedances and may damage signal fidelity.
The preferred way of transmitting high-speed data is through differential transmission signals. FIG. 1 illustrates a classic pair of differential transmission signal traces 102a, 102b on a portion of a printed circuit board 100. As illustrated, the printed circuit board 100 is formed as a plurality of layers. In the illustrative embodiment, the printed circuit board 100 includes a ground plane 104 layered over a substrate 105, a dielectric 103 layered over the ground plane 104, traces 102a, 102b layered over the dielectric 103, and a solder mask 106 layered over the traces 102a, 102b and exposed surfaces of the dielectric 103. In such a layout, there are a number of critical parameters that affect the impedance of the signal path. These parameters include trace width 110, trace separation 111, trace thickness 112, and dielectric constants of the solder mask and board material. These parameters influence the inductance, capacitance, and resistance (skin effect and DC) of the traces, which combine to determine the transmission impedance. It is generally desireable to control this value across the entire run of each trace 102a, 102b. 
In some higher speed designs it is also important to control the symmetry of the traces. FIG. 2A illustrates an ideal dense circuit layout with trces 102a–102f having identical lengths and 50 mils apart before any test targets have been added to the layout. However, routing signals on a crowded printed circuit board necessitates curves and bends in the path, which makes matching lengths and symmetries more difficult. In some cases, series components (such as series terminations or DC blocking capacitors) may be included in the path, and these have dimensions that differ from the layout parameters. Signals may also have to traverse connectors, which add to the difficulties.
Another trend is toward higher and higher density boards, which are also layout critical. When traditional test probe targets are added to a high-density board, the board layout is generally disturbed, as shown in FIGS. 2B and 2C in which adding two test probe targets to 2 nodes necessitates moving at least 4 others out of the way. Such changes to high-density boards in many cases, may not be practical, as there may not be any room to move traces. If any of the signal traces also happen to be high-frequency signal traces, then the bends needed to re-route them may also have a negative performance impact as well as the negative effects of the conventional target itself.
Additional difficulties arise when testing is considered. Testing requires tester access to circuit traces at particular probe targets. Layout rules typically require test targets to be at least 50 mils apart and may require the diameter of the test point targets to greatly exceed the width of the traces. FIG. 2B illustrates test targets 115a, 115b symmetrically positioned 50 mils apart on the differential signal traces 102a, 102b. FIG. 2C illustrates test targets 115a, 115b arranged asymmetrically, but at least 50 mils apart, on the differential signal traces 102a, 102b. 
The positioning of test targets 115a, 115b can be problematic. In many cases the need to keep a minimum separation between targets (typically 50 mils, minimum) is in direct conflict with controlled impedance layout rules. These conflicts lead to either a compromise in controlled impedance integrity, or a forced reduction in target placement with a resulting reduction in testability.
While high-speed printed circuit boards are one example of layout-critical circuits, another more general case is that of high-density boards. Adding conventional probe targets to a high-density board will most likely disturb the layout as seen in FIGS. 2B–2C. In FIGS. 2B–2C, adding test points to just 2 nodes necessitates moving 4 other traces out of the way. In many cases, in a high-density circuit design, this may be impractical, if not impossible, as there may not be any room to move these 6 traces in a crowded circuit layout. If any traces are also high-frequency signal traces, then the re-routing may have an additional negative performance impact as well as the negative effects to the optimal circuit layout itself.
As signal speeds continue to rise and board densities increase, this problem will only get worse.